--
-- VHDL Architecture audio.SMconverter.Arch
--
-- Created:
--          by - marry608.student (olympen-13.edu.isy.liu.se)
--          at - 10:57:11 09/29/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.numeric_std.all;

ENTITY SMconverter IS
  PORT( 
  AD_right_out           : IN     std_logic_vector(23 downto 0);
  AD_left_out            : IN     std_logic_vector(23 downto 0);
  sys_clk                : IN     std_logic;
  stereo_out_right       : OUT    std_logic_vector(23 downto 0);
  stereo_out_left        : OUT    std_logic_vector(23 downto 0);
  IFFT_in                : IN     integer;
  FFT_out                : OUT    integer
  );
  
  -- Declarations
  
END SMconverter ;

--
ARCHITECTURE Arch OF SMconverter IS
signal rigth_value:integer;
signal left_value:integer;
signal bit_value:integer;
signal conversion:bit;
signal FFT_out_right:integer;
signal FFT_out_left:integer;
BEGIN
  
  stereo_mono:PROCESS(sys_clk)
  BEGIN
    if rising_edge(sys_clk) then
      if conversion = '0' then
      FFT_out_right<=TO_INTEGER(AD_right_out);
      FFT_out_left<=TO_INTEGER(AD_left_out);
      conversion<='1';
      elsif conversion ='1' then
        FFT_out<=(FFT_out_right + FFT_out_left) / 2;
        conversion<='0';
      end if;
    --  for i in in1'length downto 0 loop
--        if in1(i) = '1' then 
--          right_value <= right_value + bit_value; 
--        end if;
--        if in2(i) = '1' then
--          left_value <= left_value + bit_value;
--        end if;                
--        bit_value <= bit_value * 2;
--      end loop;
--      FFT_out<=(left_value+right_value)/2;
    end if;
  END PROCESS;
  
  mono_stereo:PROCESS(sys_clk)
  BEGIN
    if rising_edge(sys_clk) then
      stereo_out_right<=std_logic_vector(to_unsigned(IFFT_in,stereo_out_right'length));
      stereo_out_left <=std_logic_vector(to_unsigned(IFFT_in,stereo_out_left'length));
    end if;
  END PROCESS;
END ARCHITECTURE Arch;


